VLSI - ASIC Digital Design FAQs

How to share data in between the linux distros and windows OS?

2009-11-03T19:40:00.000-08:00

Whenever you install multi operating system on your machine, the first problem after the correct installation of everything you face is "How to share the data in between of them?".Note: During the installation of the multi operating system, you need to leave a partition to use for data sharing in between the multi OSs.Make that left partition, for data sharing, as FAT32.Windows will detect that

How to install Multi operating systems (Solaris, RHEL, CENTOS, FEDORA, SUSE) on single or multiple hard disks? -- Part3

2009-06-07T13:33:00.000-07:00

Fedora 10 :-Note:Don't forget that Fedora always need / (root) label to get installed, so change the other OS's labels to something else as /1 or /12 or /123, etc. by using any partition software like paragon partition software or something else.Change the menu.lst of the OS, which is in MBR, accordingly.Now start the installation of Fedora 10:Everything will be almost same as earlier

How to install Multi operating systems (Solaris, RHEL, CENTOS, FEDORA, SUSE) on single or multiple hard disks? -- Part2

2009-05-24T10:11:00.000-07:00

So till so far we are done with Solaris & RHEL.Note: If in case, you had not mentioned during RHEL installation about Solaris, even though you need not to worry. Let the system get booted in RHEL and edit this file /boot/grub/menu.lstYou need to just add the chain loader command for Solaris grub after the RHEL in menu.lst file, save it and reboot the system.For Example (as in this case) :#######

How to install Multi operating systems (Solaris, RHEL, CENTOS, FEDORA, SUSE) on single or multiple hard disks? -- Part1

2009-05-19T10:20:00.000-07:00

First of all, few facts:Hard disk can only be partitioned in four primary partition.Solaris & Windows need primary partitions to get installed.What we are going to do:We are going to install the following Operating Systems on a "Blank SATA Hard Disk":Solaris 10RHEL 5.3CENTOS 5.2Fedora 10SUSE 11.1Get prepared to start the installation:Get all operating systems installation CDs or DVDs.Don't forget

What is the netlistless floorplan? And what is the use of it?

2008-09-20T12:45:00.000-07:00

Netlistless floorplan is a dummy floorplan with all available information and guesses by the previous experiences, to have a look into the possible coming difficulties in making the chip a way to Fab.Generally we start this activity at the stage of synthesis. When the synthesis is going on, at the same time the team comes up with a rough floorplan. Generally the design related strategies get

In most of the design, generally memory block has very less time margin to meet setup or hold requirements, then how you'll be able to meet timings?

2008-08-09T12:51:00.000-07:00

By putting a latch before the memory or you can say by applying "time borrowing" concept. But still designers don’t prefer in simple designs to place latch everywhere, where they are not meeting timings, since then analysis will be more complicated.Next Question:What is the netlistless floorplan? And what is the use of it?Get the answer in detail by next weekend (15th Aug), till then think over

What is the Physical Design? What are the various steps included in the whole process?

2008-06-27T11:45:00.000-07:00

"Physical Design" includes all the tasks needed to build a silicon chip from design netlist to final GDSII layout.Compared to design capture, simulation, and logic synthesis (which are called front-end activities), physical design is referred to as back-end work.In other words, physical design covers the tasks necessary to turn the design from a logic entity into a physical entity. It starts from

Regarding SKEW and CLK Timeperiod

2008-05-27T06:43:00.001-07:00

On Thu, May 22, 2008 at 9:32 PM, helio vlsi wrote:Hi *******,Yes, its possible. Your skew can be greater than clock period.But i think you'll never able to see it in your design, until unless you make the design purposefully to give that much of skew or when someone do the CTS, who doesn't know it at all.No tool will give you that much of skew, until unless you are forcing

Think and get back by this weekend for answers

2008-05-13T12:13:00.000-07:00

Why Setup and Hold? Or What is the reason behind there existence ?What is negative setup and why we use that?In most of the design, generally memory block has very less time margin to meet setup or hold requirements. In that case how you'll be able to meet the timing?What is the difference between SOC and ASIC ? Is there, really, any?When we go for the Full Custom and when for Semi Custom Design?

What is Standard Delay Format (SDF)?

2008-05-12T12:30:00.001-07:00

SDF stands for the “Standard Delay Format”. It stores the timing data generated by EDA tools for use at any stage in the design process. It can be used anywhere in the flow as to import or export the timing information about design. The data in the SDF file is represented in tool independent way and can include: Delays: Module path delay, device delay, interconnects delay and port

What is Wire Load Model (WLM)?

2008-05-12T12:17:00.000-07:00

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it.Prior to Routing stage, net parasitics and delays cannot be accurately determined. So, to predict delay we need to know the parasitics associated with interconnect/net:1. Net Capacitance2. Net ResistanceBut at the pre-routing stage, we know only the fanout of

Basic STA Part-3

2008-05-10T06:52:00.000-07:00

Net and Cell Timing Arcs: The actual path delay is the sum of net and cell delays along the timing pathNet/Interconnect Delay and Cell/Gate Delay:“Net/Interconnect Delay” refers to the total time needed to charge or discharge all the parasitics of a given net. Total net parasitics are affected by 1. Net length 2. Net fanout“Cell/

VLSI - ASIC FLOW - Part-2

2008-05-09T11:26:00.000-07:00

I think, anybody who is going to start the ASIC flow should know the Characteristics of the Good ASIC Design Flow. Characteristics of Good design flow: Design flow should have the flexibility to deal with the new challenges, which keep coming with changing technology, with minimum changes in it. As the EDA industry is also growing, new tools are emerging at an accelerated speed,

Please Pay Attention:

2008-05-04T01:07:00.000-07:00

It's a bit difficult to make questions and keep answering those. Better, Please put your queries and suggestions as comment here or mail me at vlsihelio@gmail.com and get the answers by the next weekend.Since i also keep updating both of the other blogs, i.e. Physical Design (VLSI - ASIC) & STA - Static Timing Analysis (VLSI - ASIC), along going through my hectic work schedule, with new posts. So

BASIC STA Part-2

2008-05-03T00:27:00.000-07:00

Timing Violations:Setup or Hold violation: Leads to improper operation of the flip flop and the connected components, it can result in missed data or ignored actions.The output of the flip flop goes into a state of metastability in the case of Setup/Hold violations. Recovery and Removal Violations : Violations of Preset and Clear signal with respect to the Clock.

VLSI - ASIC FLOW - Part-1

2008-05-01T05:35:00.000-07:00

Where it all got started?Existence of “NEED” assures MARKET and so CUSTOMERS, DEMAND and SUPPLY. And this force drives everything including our technology also. In VLSI industry, “Time to Market” is the most important factor; you can “DELAY” or “EXIST”. It’s very rare, when you can have both choices at a time. Reasons can have a broad spectrum, but the consequences are almost limited to

BASIC STA Part-1

2008-04-28T12:45:00.000-07:00

Timing Analysis: Timing analysis is necessary to calculate the design’s system performance, describes the chips specification, accounts for chip pad loading, helps in achieving clock speed and above all of the reasons, determines if the chip works in two contrast places, like Sahara and Switzerland. Types of timing analysis: 1. Dynamic timing analysis (DTA) 2. Static timing analysis

INTRODUCTION TO ASIC - Part-2

2008-04-18T15:15:00.000-07:00

Field Programmable Gate Arrays: • None of the layers is customized. • Basic logic cells and interconnect can be programmed. • Basic cells can be SRAM based, Flash Memory based or fuse-based (One time programmable) Advantages & Disadvantages of FPGA: Advantages: • A shorter time to market • Ability to re-program in the field to fix bugs •

INTRODUCTION TO ASIC - Part-1

2008-04-18T13:11:00.000-07:00

Evolution of VLSI: What is an ASIC? • Application-specific integrated circuit • Customized for a particular use customized for a particular use, rather than intended for general-purpose use • For example, a chip designed solely to run a cell phone is an ASIC. [Not ASICs: General-purpose processors, memory chips and other standard components] •Dedicated to single function, or limited range of

Physical Design For Novices

2008-04-04T12:19:00.000-07:00

Welcome to the Physical DesignFirst of all what are the basics you need to know:At BE level:Device PhysicsDigital Design (Basic & Advanced)Analog CircuitsCircuit TheoryBasic CMOS TheoryRecommended Books:Integrated Electronics - Millman & HalkiasDigital Design - Morris ManoDigital Logic & Computer Design - Morris ManoPrinciples of CMOS Vlsi Design - Neil Weste Note: Whatever are mentioned