What is the netlistless floorplan? And what is the use of it?

Netlistless floorplan is a dummy floorplan with all available information and guesses by the previous experiences, to have a look into the possible coming difficulties in making the chip a way to Fab.
Generally we start this activity at the stage of synthesis. When the synthesis is going on, at the same time the team comes up with a rough floorplan. Generally the design related strategies get almost completed by the time of synthesis, anyway the possibility of minor changes are always there and at any stage.
As in any big design generally there will be memory blocks, some big or small hard and soft macros and like this some more blocks where we know there will not be much changes in their shapes and positions, so now we can come up with a rough floorplan. Obviously there will be a lot of changes in the whole floorplan afterwards but just to keep ourselves always ready for the worst situations we use to have a look into the future in various ways n aspects.
Since the things are still not completed so the tools will give alots of error in analyzing the things but at that time you need to know that why it’s coming and if possible then make some temporary fixes and proceed. Some times we cheat the tools also by various ways.
We generally use this netlistless floorplan for power planning and afterward, static IR drop analysis, just to have an idea about the problems which may screw the things badly.

In most of the design, generally memory block has very less time margin to meet setup or hold requirements, then how you'll be able to meet timings?

By putting a latch before the memory or you can say by applying "time borrowing" concept.
But still designers don’t prefer in simple designs to place latch everywhere, where they are not meeting timings, since then analysis will be more complicated.

Next Question:
What is the netlistless floorplan? And what is the use of it?
Get the answer in detail by next weekend (15th Aug), till then think over it.

What is the Physical Design? What are the various steps included in the whole process?

"Physical Design" includes all the tasks needed to build a silicon chip from design netlist to final GDSII layout.

Compared to design capture, simulation, and logic synthesis (which are called front-end activities), physical design is referred to as back-end work.

In other words, physical design covers the tasks necessary to turn the design from a logic entity into a physical entity. It starts from the netlist, which is generated from the logic synthesis. However, the physical design can also include the task of RTL logic synthesis since there is an ever-increasing tie between the logic synthesis and the physical layout. The term physical synthesis reflects this fact.

The list below shows roughly the major tasks in the physical design domain:

1. Logic synthesis
2. DFT insertion
3. Electric rules check (ERC) on gate-level netlist
4. Floorplan
5. Die size
6. I/O structure
7. Design partition
8. Macro placement
9. Power distribution structure
10. Clock distribution structure
11. Preliminary check
12. IR drop
13. ESD
14. EM
15. Place and route
16. Parasitic extraction and reduction
17. SDF generation
18. Various checks
19. Static timing analysis
20. Cross talk analysis
21. IR drop analysis
22. Electron migration analysis
23. Gate oxide integrity check
24. ESD/latch-up check
25. Efuse check
26. Antenna check
27. Final layout generation
28. Manufacturing rule check, LVS check
29. Pattern generation

Regarding SKEW and CLK Timeperiod

On Thu, May 22, 2008 at 9:32 PM, helio vlsi <vlsihelio@gmail.com> wrote:

Hi *******,
Yes, its possible. Your skew can be greater than clock period.

But i think you'll never able to see it in your design, until unless you make the design purposefully to give that much of skew or when someone do the CTS, who doesn't know it at all.

No tool will give you that much of skew, until unless you are forcing it to do like that.

But STA tool will take that in different manner, and it will not recognize that much of skew. Simply it will do the analysis on the previous edges.

Ok, do one thing, take a clock as reference and then take another one which is delaying by more than a clock. And then do the setup & hold check. Analyze the various scenarios by shifting it in left n right, i think u'll get the point.

Don't forget, tool doesn't understand anything until unless you aren't defining it in constraints.

Try n get back if still you have any doubt in your mind.
Thanks for query.

Regards
Helio

On Wed, May 21, 2008 at 1:16 PM, ****** <**********@gmail.com> wrote:

Hi helio,

I am ******. I have doubt in STA.
Is there any chance of clock skew being greater than or equal to the timeperiod of the clock? If so,what are the effects?

Any help would greatly appreciated.
Thanks in advance.

--
" I don't have the LICENSE to kill ;
But then again I can't change my looks."


lots of love

******

Think and get back by this weekend for answers

1. Why Setup and Hold? Or What is the reason behind there existence ?
2. What is negative setup and why we use that?
3. In most of the design, generally memory block has very less time margin to meet setup or hold requirements. In that case how you'll be able to meet the timing?
4. What is the difference between SOC and ASIC ? Is there, really, any?
5. When we go for the Full Custom and when for Semi Custom Design? Why?
6. What is the Physical Design?
   
7. Why it's necessary or what is its importance in the whole flow?
8. What are the various steps include in the whole process of Physical Design?
9. What are the necessary informations, we need to start the Physical Design of any project?

References:

1. www.extremephysicaldesign.blogspot.com
2. www.vlsi-sta.blogspot.com

Note: Thanks for your interest in making this blog more interactive. But still, very few responses.
Send your queries, asap. Mail me at vlsihelio@gmail.com or post a comment.

Don't hesitate to ask and never forget, "Learning is the only process where all small n stupid questions are more worthier than the smart ones".

What is Standard Delay Format (SDF)?

SDF stands for the “Standard Delay Format”.

It stores the timing data generated by EDA tools for use at any stage in the design process. It can be used anywhere in the flow as to import or export the timing information about design.

The data in the SDF file is represented in tool independent way and can include:

1. Delays: Module path delay, device delay, interconnects delay and port delay.
2. Timing checks: Setup, hold, recovery, removal, skew, width, period and no change.
3. Timing constraints: Path, skew, period, sum and diff.
4. Timing environment: Intended operating timing environment.
5. Incremental and absolute delays.
6. Conditional and unconditional module path delays and timing checks.
7. Design/Instance specific or type/library specific data.
8. Scaling, environmental and technology parameters like, Process variations, temperature, voltage and wire load models.

Throughout the design process, you can use several different sdf files. Some of these files can contain pre layout timing data. Others can contain path constraint or post layout timing data.

The name of each sdf file is generated (determined) by EDA tool. There are no conventions for naming SDF files.

What is Wire Load Model (WLM)?

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it.

Prior to Routing stage, net parasitics and delays cannot be accurately determined. So, to predict delay we need to know the parasitics associated with interconnect/net:
1. Net Capacitance
2. Net Resistance

But at the pre-routing stage, we know only the fanout of net and the size of the block that the net belongs to. We can’t predict the resistance of the various pieces of the interconnect path, since we don’t know the shape of interconnect for a net.

However, we can estimate the total length of the interconnect and thus estimate the total capacitance. We estimate interconnect length by collecting statistics from previously routed chips and analyzing the results. From these statistics we create tables that predict the interconnect capacitance as a function of net fanout and block size.

WLM can come from your library or from a floor planning tool. It is the method to initially estimate your delays and is usually overly pessimistic.
WLM analysis has three modes:
1. Top: use the WLM for the top module to calculate delays for all modules.
2. Enclosed: use the WLM of the module which completely encloses the net to compute delay for that net.
3. Segmented: if a net goes across several WLM, use the WLM that corresponds to that portion of the net which it encloses only.


So, we can say, wireload model is basically a set of tables of
1. Net fanout vs Load
2. Net fanout vs Resistance
3. Net fanout vs Area

And it is required for compile to estimate interconnect wiring delays .In this all attributes like area, resistance, capacitance, slope and fan-out are given per unit length.

Example:

How are net resistance and capacitance calculated with Wireload Models?

• Simple Table Lookup is performed

Some Important facts about WLM:

1. There are no standards for the wire load tables themselves, but there are some standards for their use and for presenting the extracted loads.
2. Wire load tables often present loads in terms of a standard load that is usually the input capacitance of a two input NAND gate with a 1X (default) drive strength.

Basic STA Part-3

Net and Cell Timing Arcs:

The actual path delay is the sum of net and cell delays along the timing path

Net/Interconnect Delay and Cell/Gate Delay:

“Net/Interconnect Delay” refers to the total time needed to charge or discharge all the parasitics of a given net.

Total net parasitics are affected by

1. Net length

2. Net fanout

“Cell/Gate delay” refers to the total time needed to reach the signal from cell input the output

Total cell delay affected by

1. Slew rate

2. Input Capacitance

Net Delay Calculation:

Prior routing stage we use Wire Load Model to estimate the delay and after routing we use the real post routed delay information for static timing analysis.

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it.

It comes from your library or from a floorplanning tool. It is the method to initially estimate your delays and is usually overly pessimistic.

Cell Delay Calculation

Prior to Routing, cell delays are calculated from tables in the technology library. The tables are commonly indexed by input transition versus total output loading

For Example: As shown in below figure, if input transition is of 0 ns and the total output load is 0.4 fF, then the cell delay will be 6 ps.

Now you know how we do the pre-layout STA and from where we get the delay values. But can you compare it with post layout STA and why we do that?

Here few things are mentioned, I think quite enough to start thinking. Later on, we’ll discuss this in detail.

Clock Source latency and Network latency

So the Clock source latency is the delay from the oscillator to the clock pin of the chip, and the Clock network latency is the delay between the clock pin of the chip to the flop.

Slack

Slack is generally defined as the difference between the Required Times (RT) and Arrival Times (AT) at an end point.

Arrival time means actual value of time getting by tool from from level one to end of level

Required arrival time (RT) is the time before which a signal must arrive to avoid a timing violation.

STEP1: Calculate timing level for each node

STEP2: Calculate AT from level 1 to level n

Assumptions:

1. Input arrival time of 1
   
2. Wire delay 0.2, cell delay 0.5
   
3. Blue colored numbers are showing levels.
   
4. Green colored numbers are showing Arrival times.
   
5. Red colored numbers are showing Required times.
   
6. Purple colored numbers are showing respective Slacks.

Calculation of RT from level n to level 1

Assumptions:

Output required time of 2.8

Gate delay 0.5, wire delay 0.5

Calculation of Slack

Slack =RT –AT

Rectification of Violations:

There are so many methods and methodologies which are followed by the tools and the designers.

Few of them are mentioned here. Don’t predict that these all methods are followed by the designer itself, nowadays tools are smart enough to use these to meet timings.

Swapping pins:

Swap connections on cumulative pins or among equivalent nets. As you can see in the below given example, how it helps to meet timings.

Resize cell:

1. Up size: If fan-out and Capacitance loading is more
   
2. Down size: If fanout and load is less.

Buffering:

We use buffering at various stages in the whole flow, so many times,

1. To improve the signal strength
2. To provide delay

Cloning:

Cloning is a good method to distribute the load and to improve the signal strength.

Re-design Fanout Tree:

This method is also used to meet timing, as you can see the longest path in the first design is of 5 (top most, in right side of both design, AND is of 3). But by redesigning it, we can achieve the longest path of 4.

Re-design Fan-in Tree:

Decomposition:

Requirements in the perspective of EDA tools:

Inputs & Outputs of STA

Inputs

Netlist (.v): The gate level netlist, having circuit description.

1. Constraints (.sdc): Synopsys Design Constraint file. It contains all the timing related information about the design. Includes the Clock definition (Created clock, generated clock, Virtual clock), Uncertainty (Jitter, Skew, Extra margin), IO Delays, False paths, Multi-cycle paths, Max trans, Max fanout, Max cap, Fanout load.
2. SDF (.sdf): Standard Delay Format File containing back-annotated delays.

OR

4. Standard Parasitic Exchange Format (.spef): These are the parasitic of the design extracted from physical design tools.
5. Liberty File (.lib): The delay model of every cell in the library.

• Outputs

Reports: Different timing paths reports, which can be used for debugging.

Various tools used in STA

1. Prime Time (PT) - Synopsys

2. Design Time (DT) - Synopsys

3. Nano Time - Synopsys

4. Path Mill - Synopsys

5. ETS - Cadence

6. Pearl - Cadence

7. Velocity - Mentor Graphics

8. Eins Timer - IBM

9. Eins TLT - IBM

10. Motive - Viewlogic (Now owned by Synopsys)

11. Time Craft - Incentia

VLSI - ASIC FLOW - Part-2

I think, anybody who is going to start the ASIC flow should know the Characteristics of the Good ASIC Design Flow.

Characteristics of Good design flow:

1. Design flow should have the flexibility to deal with the new challenges, which keep coming with changing technology, with minimum changes in it.
2. As the EDA industry is also growing, new tools are emerging at an accelerated speed, so the design flow should have the ability to absorb the latest developments easily.
3. Design flow should also have the capability of handling large, complicated designs and small, simpler designs differently.
4. There should be flexibility to allow some major steps to be executed on their own or outside of the flow, as place n route, sta, etc.
5. Design flow should be friendly to engineering change order (ECO).
6. Check function of the design flow must be robust, sometimes even at the expense of efficiency.

Design of Specification:

To design the specification you need few basic things to know, about the targeted product, as

1. Function: What is expected from the ASIC or what it supposed to do? So, here you will decide the functionality of the product at top level hierarchy.
2. Performance: What will be the speed, how much power it will consume, how much silicon area it’ll take to implement?
3. I/O requirements: How will the ASIC fit together with the system? So you need to get the requirements of the Inputs and Outputs.
4. Special Requirements (if any): If the targeted product has any special requirement like Low Power, or has some specific parameters to fit in. In that case we need to define our specification in that manner.

Feasibility Check:

So now you have designed the specifications but are they feasible?

You need to cross check all of the specifications very carefully with all of your project constraints (Cost, Design Time, etc.) to reduce the chances of failure.

Since, in the VLSI industry, in most of the cases, you’ll find the condition of “no back looking” .

1. For most of the projects the condition is “we have never done it, so we don’t know exactly”.

2. Since, we have experience from earlier projects, so we can make small experiments to estimate performance and can choose appropriate technology.

Once we get confirmed with the feasibility checks, then only we can proceed further.

After getting the specification, now it’s the time to act. So once you have the specs then you need to decide the way that in how many ways you can achieve it, and which one is the best suitable way.

When it comes to the suitability, then it includes everything, from Risks to Cost, Time to chances of Failure.

Whole process has lots of complication and in the same time, Time to Market factor is also there. So you need to be very careful while deciding the way to achieve.

Design of Architecture:

As you know, in the whole flow there are so many steps and in so many ways we can achieve the goal in better way.

Here I am taking the most common flow of a small design, but during while, will discuss all related issues and after that we’ll see the bigger picture of the ASIC, that is SOC.

So first you design the Block at schematic level by using various combinational and sequential elements. And then you check it on simulation tools, by passing various test cases. And then you proceed further.

But this can be also done with just an idea of implementation on paper with the help of block diagrams and then we start with HDL, i.e. Hardware Description Languages.

Block Diagram:

It is an iterative process. For that we need to follow some steps, they are

1. Identify blocks: First we should get all the required information to perform the functionality.
   
2. Visualize structure: Now determine the various connections between the blocks.
   
3. Critical paths: Determine the blocks, which are most critical in terms of speed, area or power.
   
4. Divide and Conquer: Draw sub-block diagrams with more details.

During the architectural transformations, we need to take care of the overall efficiency of the design, which is based on the performance parameters:

1. Area (mm2)
   
2. Clock rate (MHz)
   
3. Throughput (data/sec)
   
4. Latency (num clock cycles)

Parallelization:

If we consider the parallelization in the design to achieve the targeted efficiency, that will result in more computations, with increase in area and throughput but clock and latency will not change.

For example:

If we use two parallel blocks, that will result in

1. Double area
   
2. Double throughput
   
3. Same clock
   
4. Same latency

Pipelining:

If we are consider the pipelining, then that will increase the speed of the computation, with increased area, clock, throughput and latency.

For example:

If we introduce one pipeline stage, that will result in

1. Little increase in area
   
2. Double clock
   
3. Double throughput
   
4. Double latency

Iterative Decomposition:

If we consider the iterative decomposition in the design, that will take more clock cycles but in lieu of that we will be able to achieve some good results in terms of area and throughput.

For example:

If we can perform the operation in two iterations, then

1. Area halves
   
2. Clock stays same
   
3. Throughput halves
   
4. Latency doubles

Please Pay Attention:

It's a bit difficult to make questions and keep answering those. Better, Please put your queries and suggestions as comment here or mail me at vlsihelio@gmail.com and get the answers by the next weekend.

Since i also keep updating both of the other blogs, i.e. Physical Design (VLSI - ASIC) & STA - Static Timing Analysis (VLSI - ASIC), along going through my hectic work schedule, with new posts. So, usually, i run out off time.

As far as Industry oriented questions and issues are concerned, i'll keep updating you, as soon as i'll get some time for the same.

Note: Before putting queries, please have a look of both of these blogs, may be the answers are already there.

Physical Design (VLSI - ASIC)
STA - Static Timing Analysis (VLSI - ASIC)

BASIC STA Part-2

Timing Violations:

• Setup or Hold violation:

1. Leads to improper operation of the flip flop and the connected components, it can result in missed data or ignored actions.
2. The output of the flip flop goes into a state of metastability in the case of Setup/Hold violations.

• Recovery and Removal Violations :

1. Violations of Preset and Clear signal with respect to the Clock.

Setup Time:

• The time required for the input data to be stable before the triggering clock edge.
• So, Set-up check establishes that the path is fast enough for the desired clock frequency.

Hold Time:

• The time required for the data to remain stable after the triggering clock edge.
• So, hold check ensures that the path is not too fast so that data is not passed through.

Why Setup & Hold?

1. Setup & Hold times are because of the intrinsic delays of the flip flop. Intrinsic delays are the actual delays of the transistors inside the cell.
2. Setup and Hold are the times required for charging the capacitances present inside in cell.

Delay of an Inverter:

t = Rp * C

The delay is decided by the resistance of Pmos and the output capacitance.

The product ‘RC’ is called the “TIME CONSTANT”. This determines the delay of the cell.

When Vo = Logic ‘1’ t = Rn * C

The delay is decided by the resistance of Nmos and the output capacitance.

How to remove Setup & Hold violations:

• To solve setup violation

1. By optimizing and restructuring the combinational logic between the flops of design. In big designs, we dont do this by ourselves, generally tool does this for us. And what are the ways that tool follows for the same? We'll discuss that in next post.

2. By using “Tweak flops” to offer less setup delay. Since, Tweak launch-flop have better slew at the clock pin and this makes CK->Q of launch flop faster, so that it helps in fixing setup violations.

3. By using Useful- skews.

• To solve Hold Violations

1. By adding delay/buffer cell. Since the simple buffer offers less delay, so we use special Delay cells whose functionality remains same, i.e. Y=A, but with more delay.

2. By providing delay to the launch flop clock.

3. Where the hold time requirement is huge, we can use Lock-up Latches also.

Few GOOGLIES for you:

1. What is negative setup? And where we use that?
2. In most of the design, generally memory block has very less time margin to meet setup or hold requirements. In that case how you'll be able to meet the timing?

Note: For more faqs, keep visiting http://vlsifaqs.blogspot.com

STA: Critical terms

1. Critical path: The path between an input and an output with the maximum delay.
2. Recovery time: It is the minimum time that an asynchronous control must be stable before the clock active-edge transition.
3. Removal time: It is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.

Jitter : Variation in period from clock source (PLL)

Insertion Delay

• The delay between the clock root pin and clock sink pin of the flip flop

Glitch- A glitch is a short-lived fault in a system.

• An electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit

Input Delay:

Output Delay:

Single Cycle Paths:

• By default, static timing tools assume all timing paths to be single cycle paths

There could be exceptions defined to the above behavior:

1. Multi-cycle paths
2. False paths

Multi-Cycle Paths:

• Those paths that require more than one clock period for execution are called as multi-cycle paths.

• It’s essential that multi-cycle paths in the design be identified both for synthesis and STA.

False Paths:

• A path that can never be sensitized in the actual circuit
• These paths are those that are logically/functionally impossible
• The goal in static timing analysis is to do timing analysis on all “true” timing paths, these paths are excluded from timing analysis.

Combinational Loop:

• Most STA’s can’t leave combinational loops in the design, because a race condition will occur.

GOOD ONE:
If i am not defining the False or Multicycle paths or Combinational Loops or Input/Output Delay in my constraint file (.sdc). In that case, what can be the effects you will find in your reports? (Analyze this one by one.)

Note: For more faqs, keep visiting http://vlsifaqs.blogspot.com

Clock skews (timing skew):

• Clock signal in synchronous circuits arrives at different components at different times.

Clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Reasons for the Skew:

1. Wire-interconnect length
2. Temperature variations
3. Variation in intermediate devices
4. Capacitive coupling
5. Material imperfections

Two Types of Clock Skew:

1. Negative skew
2. Positive skew

Positive skew:

• Occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Negative skew:

• Is the opposite:- the receiving register gets the clock earlier than the sending register.

VLSI - ASIC FLOW - Part-1

Where it all got started?

Existence of “NEED” assures MARKET and so CUSTOMERS, DEMAND and SUPPLY.

And this force drives everything including our technology also.

In VLSI industry, “Time to Market” is the most important factor; you can “DELAY” or “EXIST”.

It’s very rare, when you can have both choices at a time.

Reasons can have a broad spectrum, but the consequences are almost limited to these parameters.

Current scenario of the industry shows that the things have got that much critical & complex, as well, that it’s almost impossible for a single company to get all jobs done, alone.

So they outsource some part of the project, there arises the concept of sub-chip level development.

But in some exceptional cases, there are few companies, who work alone and get everything done in house only.

In ASIC (Application Specific Integrated Circuit) or SOC (System on Chip) implementation, there are two main categories, “ Full custom flow” or “Semi custom flow”.

For the further reading on the same, please refer “ASIC- Sebastian Smith”.

As of now, in short, for Full custom, we need to create a specific library for the targeted product, but in Semi custom we use the already existed library to implement the product.

According to the targeted product the flow keeps changing by time, as well according to the technology.

So the question arises here, what is the difference b/w ASIC and SOC?

Keep scratching your head, I’ll discuss that later, may be in my next post.

Now, Full chip and Sub chip Design. Anyway, while discussing the complete flow I’ll be discussing both of these things relatively.

But as of now, A Full chip can have many Sub chips (Macros/Blocks).
Here is a rough hierarchy of the chip, hopes will be a bit helpful.

The flow, I am going to consider is:

*ASIC (Full Chip/Sub-chip)/SOC

1. Specification
2. Architecture
3. Lib Preparation
4. IP implementation/Reuse and Rtl Coding
5. Simulation & Verification
6. Synopsys Design Constraints (SDC)
7. Synthesis
8. Design for Testability (DFT)
9. Static Timing Analysis (STA)
10. Floorplanning
11. Power planning
12. Placement
13. Clock Tree Synthesis (CTS)
14. Routing
15. RC Extraction
16. Design Rule Check (DRC) & Layout Vs Schematic (LVS)
17. Post Route STA
18. Signal Integrity (SI) Analysis
19. IR drop Analysis
20. Noise Analysis
21. Signoff

Note: I have tried to keep every necessary part of the design in the flow. But even though, if you think some thing else should also be added, then, please let me know via comments.

Before going for the flow, I want to discuss few basic things first.

What is Hardware Design?

Physically implementing an idea, a function and a system in hardware.
For any such kind of implementation we need to find the optimal balance between:

1. Cost / Area
2. Speed / Throughput
3. Energy Consumption / Power Density
4. Design Time

Trade-offs in Design

In the design, if you want any thing more specific then usually you need to sacrifice or, you can say, compromise with some other parameters.
So, there’s “No free lunch”.

Depending on the design, some parameters are more important and some are less.
So, you can generally sacrifice one parameter to improve the other:

1. Speed vs Area: It is possible to speed up a circuit by using larger transistors, parallel computation blocks, but then it will take more area.

2. Design time vs Performance: If we are with enough time to design, then the circuits can be optimized for higher Performance.

So, finally you need to make a lot of trade offs in the whole process of design, with different parameters like, speed, area, power, etc.

When to use ASICs?

As in the earlier posts, I have discussed the pros & cons of the ASIC. So, here just I am going in brief.

The pros:

1. Highest performance
2. Cheap for mass production

The cons:

1. Long development time
2. Not very configurable
3. Requires specialization

So overall, it depends upon our targeted product, whether we should go for the ASIC or FPGA or CPLD, etc.