BASIC STA Part-2

Timing Violations:

• Setup or Hold violation:

1. Leads to improper operation of the flip flop and the connected components, it can result in missed data or ignored actions.
2. The output of the flip flop goes into a state of metastability in the case of Setup/Hold violations.

• Recovery and Removal Violations :

1. Violations of Preset and Clear signal with respect to the Clock.

Setup Time:

• The time required for the input data to be stable before the triggering clock edge.
• So, Set-up check establishes that the path is fast enough for the desired clock frequency.

Hold Time:

• The time required for the data to remain stable after the triggering clock edge.
• So, hold check ensures that the path is not too fast so that data is not passed through.

Why Setup & Hold?

1. Setup & Hold times are because of the intrinsic delays of the flip flop. Intrinsic delays are the actual delays of the transistors inside the cell.
2. Setup and Hold are the times required for charging the capacitances present inside in cell.

Delay of an Inverter:

t = Rp * C

The delay is decided by the resistance of Pmos and the output capacitance.

The product ‘RC’ is called the “TIME CONSTANT”. This determines the delay of the cell.

When Vo = Logic ‘1’ t = Rn * C

The delay is decided by the resistance of Nmos and the output capacitance.

How to remove Setup & Hold violations:

• To solve setup violation

1. By optimizing and restructuring the combinational logic between the flops of design. In big designs, we dont do this by ourselves, generally tool does this for us. And what are the ways that tool follows for the same? We'll discuss that in next post.

2. By using “Tweak flops” to offer less setup delay. Since, Tweak launch-flop have better slew at the clock pin and this makes CK->Q of launch flop faster, so that it helps in fixing setup violations.

3. By using Useful- skews.

• To solve Hold Violations

1. By adding delay/buffer cell. Since the simple buffer offers less delay, so we use special Delay cells whose functionality remains same, i.e. Y=A, but with more delay.

2. By providing delay to the launch flop clock.

3. Where the hold time requirement is huge, we can use Lock-up Latches also.

Few GOOGLIES for you:

1. What is negative setup? And where we use that?
2. In most of the design, generally memory block has very less time margin to meet setup or hold requirements. In that case how you'll be able to meet the timing?

Note: For more faqs, keep visiting http://vlsifaqs.blogspot.com

STA: Critical terms

1. Critical path: The path between an input and an output with the maximum delay.
2. Recovery time: It is the minimum time that an asynchronous control must be stable before the clock active-edge transition.
3. Removal time: It is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.

Jitter : Variation in period from clock source (PLL)

Insertion Delay

• The delay between the clock root pin and clock sink pin of the flip flop

Glitch- A glitch is a short-lived fault in a system.

• An electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit

Input Delay:

Output Delay:

Single Cycle Paths:

• By default, static timing tools assume all timing paths to be single cycle paths

There could be exceptions defined to the above behavior:

1. Multi-cycle paths
2. False paths

Multi-Cycle Paths:

• Those paths that require more than one clock period for execution are called as multi-cycle paths.

• It’s essential that multi-cycle paths in the design be identified both for synthesis and STA.

False Paths:

• A path that can never be sensitized in the actual circuit
• These paths are those that are logically/functionally impossible
• The goal in static timing analysis is to do timing analysis on all “true” timing paths, these paths are excluded from timing analysis.

Combinational Loop:

• Most STA’s can’t leave combinational loops in the design, because a race condition will occur.

GOOD ONE:
If i am not defining the False or Multicycle paths or Combinational Loops or Input/Output Delay in my constraint file (.sdc). In that case, what can be the effects you will find in your reports? (Analyze this one by one.)

Note: For more faqs, keep visiting http://vlsifaqs.blogspot.com

Clock skews (timing skew):

• Clock signal in synchronous circuits arrives at different components at different times.

Clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Reasons for the Skew:

1. Wire-interconnect length
2. Temperature variations
3. Variation in intermediate devices
4. Capacitive coupling
5. Material imperfections

Two Types of Clock Skew:

1. Negative skew
2. Positive skew

Positive skew:

• Occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Negative skew:

• Is the opposite:- the receiving register gets the clock earlier than the sending register.

VLSI - ASIC FLOW - Part-1

Where it all got started?

Existence of “NEED” assures MARKET and so CUSTOMERS, DEMAND and SUPPLY.

And this force drives everything including our technology also.

In VLSI industry, “Time to Market” is the most important factor; you can “DELAY” or “EXIST”.

It’s very rare, when you can have both choices at a time.

Reasons can have a broad spectrum, but the consequences are almost limited to these parameters.

Current scenario of the industry shows that the things have got that much critical & complex, as well, that it’s almost impossible for a single company to get all jobs done, alone.

So they outsource some part of the project, there arises the concept of sub-chip level development.

But in some exceptional cases, there are few companies, who work alone and get everything done in house only.

In ASIC (Application Specific Integrated Circuit) or SOC (System on Chip) implementation, there are two main categories, “ Full custom flow” or “Semi custom flow”.

For the further reading on the same, please refer “ASIC- Sebastian Smith”.

As of now, in short, for Full custom, we need to create a specific library for the targeted product, but in Semi custom we use the already existed library to implement the product.

According to the targeted product the flow keeps changing by time, as well according to the technology.

So the question arises here, what is the difference b/w ASIC and SOC?

Keep scratching your head, I’ll discuss that later, may be in my next post.

Now, Full chip and Sub chip Design. Anyway, while discussing the complete flow I’ll be discussing both of these things relatively.

But as of now, A Full chip can have many Sub chips (Macros/Blocks).
Here is a rough hierarchy of the chip, hopes will be a bit helpful.

The flow, I am going to consider is:

*ASIC (Full Chip/Sub-chip)/SOC

1. Specification
2. Architecture
3. Lib Preparation
4. IP implementation/Reuse and Rtl Coding
5. Simulation & Verification
6. Synopsys Design Constraints (SDC)
7. Synthesis
8. Design for Testability (DFT)
9. Static Timing Analysis (STA)
10. Floorplanning
11. Power planning
12. Placement
13. Clock Tree Synthesis (CTS)
14. Routing
15. RC Extraction
16. Design Rule Check (DRC) & Layout Vs Schematic (LVS)
17. Post Route STA
18. Signal Integrity (SI) Analysis
19. IR drop Analysis
20. Noise Analysis
21. Signoff

Note: I have tried to keep every necessary part of the design in the flow. But even though, if you think some thing else should also be added, then, please let me know via comments.

Before going for the flow, I want to discuss few basic things first.

What is Hardware Design?

Physically implementing an idea, a function and a system in hardware.
For any such kind of implementation we need to find the optimal balance between:

1. Cost / Area
2. Speed / Throughput
3. Energy Consumption / Power Density
4. Design Time

Trade-offs in Design

In the design, if you want any thing more specific then usually you need to sacrifice or, you can say, compromise with some other parameters.
So, there’s “No free lunch”.

Depending on the design, some parameters are more important and some are less.
So, you can generally sacrifice one parameter to improve the other:

1. Speed vs Area: It is possible to speed up a circuit by using larger transistors, parallel computation blocks, but then it will take more area.

2. Design time vs Performance: If we are with enough time to design, then the circuits can be optimized for higher Performance.

So, finally you need to make a lot of trade offs in the whole process of design, with different parameters like, speed, area, power, etc.

When to use ASICs?

As in the earlier posts, I have discussed the pros & cons of the ASIC. So, here just I am going in brief.

The pros:

1. Highest performance
2. Cheap for mass production

The cons:

1. Long development time
2. Not very configurable
3. Requires specialization

So overall, it depends upon our targeted product, whether we should go for the ASIC or FPGA or CPLD, etc.

BASIC STA Part-1

Timing Analysis:

Timing analysis is necessary to calculate the design’s system performance, describes the chips specification, accounts for chip pad loading, helps in achieving clock speed and above all of the reasons, determines if the chip works in two contrast places, like Sahara and Switzerland.

Types of timing analysis:

1. Dynamic timing analysis (DTA)

2. Static timing analysis (STA)

Dynamic Timing Analysis (Gate level Simulation):

A series of vectors over a time are applied during a simulation run, simulation calculates the logic value and delays over that time. So, in that manner we check the design’s functionality with time.

Static Timing Analysis:

Static timing analysis is a method for determining if a circuit meets timing constraints without having to simulate.

So, it validates the design for desired frequency of operation, without checking the functionality of the design.

Comparison of Analysis

Dynamic timing

1. Requires exhaust set of vectors
2. Checks for both functional and timing problems
3. Requires more resources like run time, CPU memory, etc.
4. Can work with any type of Logic either synchronous or asynchronous
5. Slower as compared to STA.
6. Easy to learn

Static timing

1. Doesn't requires any set of vectors.
2. Checks for timing only.
3. Requires fewer resources than DTA.
4. Restricted to synchronous part of the design only.
5. Faster as compared to DTA.
6. Difficult to learn

Why Static timing Analysis?

1. To analyze the timing relationships of a given circuit to verify that the circuit works at the specified frequency (verification).
2. 100 % path coverage is possible because no design specific pattern is required.
3. You can’t achieve the clock speed without it.
4. All paths are assumed critical.
5. Process variation across die can be modeled.
6. Constraints and reports are concise and easy to interpret.
7. It can detect other serious problems like glitches, slow paths and clock skew.

Note: This analysis is done to provide the engineer feedback in order to help modify the design and/or modify the constraints to improve the timing quality of the design.

Place of STA in the ASIC Flow

STA involves three main steps:

1. Design is broken down into sets of timing paths.
2. Delay of each path is calculated.
3. Path delays are checked to see if timing constraints have been met.

But first some Basic STA concepts:

Timing Paths:

Each path has a startpoint and an endpoint

1. Startpoints:

Input ports (A, Q)

Clock pins of sequential devices (CLk)

2. Endpoints:

Output ports (D, Z)

Data input pins of sequential devices (D)

Basic Timing Paths

Generally recognizes five types of default timing paths:

1. Clock to setup
2. Clock to pad
3. Pad to pad
4. Pad to set up

Clock to setup:

A clock to setup path starts at flip flop clock inputs, propagates through the flip flop Q out put and any number of levels of combinational logic, and ends at non clock flip flop register inputs.

Clock to pad:

It starts at a clock input of a flip-flop, propagates through the flip-flop Q output and any number of levels of combinational logic, and ends at an output pad.

Pad to Pad :

A pad to pad path starts at an input of the chip, propagates through one or more levels of combinational logic, and end at an output pad of the chip.

Pad to Setup:

A pad to setup path starts at an input pad of chip and ends at flip flop input.