Compared to design capture, simulation, and logic synthesis (which are called front-end activities), physical design is referred to as back-end work.
In other words, physical design covers the tasks necessary to turn the design from a logic entity into a physical entity. It starts from the netlist, which is generated from the logic synthesis. However, the physical design can also include the task of RTL logic synthesis since there is an ever-increasing tie between the logic synthesis and the physical layout. The term physical synthesis reflects this fact.
The list below shows roughly the major tasks in the physical design domain:
- Logic synthesis
- DFT insertion
- Electric rules check (ERC) on gate-level netlist
- Floorplan
- Die size
- I/O structure
- Design partition
- Macro placement
- Power distribution structure
- Clock distribution structure
- Preliminary check
- IR drop
- ESD
- EM
- Place and route
- Parasitic extraction and reduction
- SDF generation
- Various checks
- Static timing analysis
- Cross talk analysis
- IR drop analysis
- Electron migration analysis
- Gate oxide integrity check
- ESD/latch-up check
- Efuse check
- Antenna check
- Final layout generation
- Manufacturing rule check, LVS check
- Pattern generation
