In most of the design, generally memory block has very less time margin to meet setup or hold requirements, then how you'll be able to meet timings?

By putting a latch before the memory or you can say by applying "time borrowing" concept.
But still designers don’t prefer in simple designs to place latch everywhere, where they are not meeting timings, since then analysis will be more complicated.

Next Question:
What is the netlistless floorplan? And what is the use of it?
Get the answer in detail by next weekend (15th Aug), till then think over it.

Regarding SKEW and CLK Timeperiod

On Thu, May 22, 2008 at 9:32 PM, helio vlsi <vlsihelio@gmail.com> wrote:

Hi *******,
Yes, its possible. Your skew can be greater than clock period.

But i think you'll never able to see it in your design, until unless you make the design purposefully to give that much of skew or when someone do the CTS, who doesn't know it at all.

No tool will give you that much of skew, until unless you are forcing it to do like that.

But STA tool will take that in different manner, and it will not recognize that much of skew. Simply it will do the analysis on the previous edges.

Ok, do one thing, take a clock as reference and then take another one which is delaying by more than a clock. And then do the setup & hold check. Analyze the various scenarios by shifting it in left n right, i think u'll get the point.

Don't forget, tool doesn't understand anything until unless you aren't defining it in constraints.

Try n get back if still you have any doubt in your mind.
Thanks for query.

Regards
Helio

On Wed, May 21, 2008 at 1:16 PM, ****** <**********@gmail.com> wrote:

Hi helio,

I am ******. I have doubt in STA.
Is there any chance of clock skew being greater than or equal to the timeperiod of the clock? If so,what are the effects?

Any help would greatly appreciated.
Thanks in advance.

--
" I don't have the LICENSE to kill ;
But then again I can't change my looks."


lots of love

******

What is Standard Delay Format (SDF)?

SDF stands for the “Standard Delay Format”.

It stores the timing data generated by EDA tools for use at any stage in the design process. It can be used anywhere in the flow as to import or export the timing information about design.

The data in the SDF file is represented in tool independent way and can include:

1. Delays: Module path delay, device delay, interconnects delay and port delay.
2. Timing checks: Setup, hold, recovery, removal, skew, width, period and no change.
3. Timing constraints: Path, skew, period, sum and diff.
4. Timing environment: Intended operating timing environment.
5. Incremental and absolute delays.
6. Conditional and unconditional module path delays and timing checks.
7. Design/Instance specific or type/library specific data.
8. Scaling, environmental and technology parameters like, Process variations, temperature, voltage and wire load models.

Throughout the design process, you can use several different sdf files. Some of these files can contain pre layout timing data. Others can contain path constraint or post layout timing data.

The name of each sdf file is generated (determined) by EDA tool. There are no conventions for naming SDF files.

What is Wire Load Model (WLM)?

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it.

Prior to Routing stage, net parasitics and delays cannot be accurately determined. So, to predict delay we need to know the parasitics associated with interconnect/net:
1. Net Capacitance
2. Net Resistance

But at the pre-routing stage, we know only the fanout of net and the size of the block that the net belongs to. We can’t predict the resistance of the various pieces of the interconnect path, since we don’t know the shape of interconnect for a net.

However, we can estimate the total length of the interconnect and thus estimate the total capacitance. We estimate interconnect length by collecting statistics from previously routed chips and analyzing the results. From these statistics we create tables that predict the interconnect capacitance as a function of net fanout and block size.

WLM can come from your library or from a floor planning tool. It is the method to initially estimate your delays and is usually overly pessimistic.
WLM analysis has three modes:
1. Top: use the WLM for the top module to calculate delays for all modules.
2. Enclosed: use the WLM of the module which completely encloses the net to compute delay for that net.
3. Segmented: if a net goes across several WLM, use the WLM that corresponds to that portion of the net which it encloses only.


So, we can say, wireload model is basically a set of tables of
1. Net fanout vs Load
2. Net fanout vs Resistance
3. Net fanout vs Area

And it is required for compile to estimate interconnect wiring delays .In this all attributes like area, resistance, capacitance, slope and fan-out are given per unit length.

Example:

How are net resistance and capacitance calculated with Wireload Models?

• Simple Table Lookup is performed

Some Important facts about WLM:

1. There are no standards for the wire load tables themselves, but there are some standards for their use and for presenting the extracted loads.
2. Wire load tables often present loads in terms of a standard load that is usually the input capacitance of a two input NAND gate with a 1X (default) drive strength.