Regarding SKEW and CLK Timeperiod

On Thu, May 22, 2008 at 9:32 PM, helio vlsi <vlsihelio@gmail.com> wrote:

Hi *******,
Yes, its possible. Your skew can be greater than clock period.

But i think you'll never able to see it in your design, until unless you make the design purposefully to give that much of skew or when someone do the CTS, who doesn't know it at all.

No tool will give you that much of skew, until unless you are forcing it to do like that.

But STA tool will take that in different manner, and it will not recognize that much of skew. Simply it will do the analysis on the previous edges.

Ok, do one thing, take a clock as reference and then take another one which is delaying by more than a clock. And then do the setup & hold check. Analyze the various scenarios by shifting it in left n right, i think u'll get the point.

Don't forget, tool doesn't understand anything until unless you aren't defining it in constraints.

Try n get back if still you have any doubt in your mind.
Thanks for query.

Regards
Helio

On Wed, May 21, 2008 at 1:16 PM, ****** <**********@gmail.com> wrote:

Hi helio,

I am ******. I have doubt in STA.
Is there any chance of clock skew being greater than or equal to the timeperiod of the clock? If so,what are the effects?

Any help would greatly appreciated.
Thanks in advance.

--
" I don't have the LICENSE to kill ;
But then again I can't change my looks."


lots of love

******