Basic STA Part-3

Net and Cell Timing Arcs:

The actual path delay is the sum of net and cell delays along the timing path

Net/Interconnect Delay and Cell/Gate Delay:

“Net/Interconnect Delay” refers to the total time needed to charge or discharge all the parasitics of a given net.

Total net parasitics are affected by

1. Net length

2. Net fanout

“Cell/Gate delay” refers to the total time needed to reach the signal from cell input the output

Total cell delay affected by

1. Slew rate

2. Input Capacitance

Net Delay Calculation:

Prior routing stage we use Wire Load Model to estimate the delay and after routing we use the real post routed delay information for static timing analysis.

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it.

It comes from your library or from a floorplanning tool. It is the method to initially estimate your delays and is usually overly pessimistic.

Cell Delay Calculation

Prior to Routing, cell delays are calculated from tables in the technology library. The tables are commonly indexed by input transition versus total output loading

For Example: As shown in below figure, if input transition is of 0 ns and the total output load is 0.4 fF, then the cell delay will be 6 ps.

Now you know how we do the pre-layout STA and from where we get the delay values. But can you compare it with post layout STA and why we do that?

Here few things are mentioned, I think quite enough to start thinking. Later on, we’ll discuss this in detail.

Clock Source latency and Network latency

So the Clock source latency is the delay from the oscillator to the clock pin of the chip, and the Clock network latency is the delay between the clock pin of the chip to the flop.

Slack

Slack is generally defined as the difference between the Required Times (RT) and Arrival Times (AT) at an end point.

Arrival time means actual value of time getting by tool from from level one to end of level

Required arrival time (RT) is the time before which a signal must arrive to avoid a timing violation.

STEP1: Calculate timing level for each node

STEP2: Calculate AT from level 1 to level n

Assumptions:

1. Input arrival time of 1
   
2. Wire delay 0.2, cell delay 0.5
   
3. Blue colored numbers are showing levels.
   
4. Green colored numbers are showing Arrival times.
   
5. Red colored numbers are showing Required times.
   
6. Purple colored numbers are showing respective Slacks.

Calculation of RT from level n to level 1

Assumptions:

Output required time of 2.8

Gate delay 0.5, wire delay 0.5

Calculation of Slack

Slack =RT –AT

Rectification of Violations:

There are so many methods and methodologies which are followed by the tools and the designers.

Few of them are mentioned here. Don’t predict that these all methods are followed by the designer itself, nowadays tools are smart enough to use these to meet timings.

Swapping pins:

Swap connections on cumulative pins or among equivalent nets. As you can see in the below given example, how it helps to meet timings.

Resize cell:

1. Up size: If fan-out and Capacitance loading is more
   
2. Down size: If fanout and load is less.

Buffering:

We use buffering at various stages in the whole flow, so many times,

1. To improve the signal strength
2. To provide delay

Cloning:

Cloning is a good method to distribute the load and to improve the signal strength.

Re-design Fanout Tree:

This method is also used to meet timing, as you can see the longest path in the first design is of 5 (top most, in right side of both design, AND is of 3). But by redesigning it, we can achieve the longest path of 4.

Re-design Fan-in Tree:

Decomposition:

Requirements in the perspective of EDA tools:

Inputs & Outputs of STA

Inputs

Netlist (.v): The gate level netlist, having circuit description.

1. Constraints (.sdc): Synopsys Design Constraint file. It contains all the timing related information about the design. Includes the Clock definition (Created clock, generated clock, Virtual clock), Uncertainty (Jitter, Skew, Extra margin), IO Delays, False paths, Multi-cycle paths, Max trans, Max fanout, Max cap, Fanout load.
2. SDF (.sdf): Standard Delay Format File containing back-annotated delays.

OR

4. Standard Parasitic Exchange Format (.spef): These are the parasitic of the design extracted from physical design tools.
5. Liberty File (.lib): The delay model of every cell in the library.

• Outputs

Reports: Different timing paths reports, which can be used for debugging.

Various tools used in STA

1. Prime Time (PT) - Synopsys

2. Design Time (DT) - Synopsys

3. Nano Time - Synopsys

4. Path Mill - Synopsys

5. ETS - Cadence

6. Pearl - Cadence

7. Velocity - Mentor Graphics

8. Eins Timer - IBM

9. Eins TLT - IBM

10. Motive - Viewlogic (Now owned by Synopsys)

11. Time Craft - Incentia

VLSI - ASIC FLOW - Part-2

I think, anybody who is going to start the ASIC flow should know the Characteristics of the Good ASIC Design Flow.

Characteristics of Good design flow:

1. Design flow should have the flexibility to deal with the new challenges, which keep coming with changing technology, with minimum changes in it.
2. As the EDA industry is also growing, new tools are emerging at an accelerated speed, so the design flow should have the ability to absorb the latest developments easily.
3. Design flow should also have the capability of handling large, complicated designs and small, simpler designs differently.
4. There should be flexibility to allow some major steps to be executed on their own or outside of the flow, as place n route, sta, etc.
5. Design flow should be friendly to engineering change order (ECO).
6. Check function of the design flow must be robust, sometimes even at the expense of efficiency.

Design of Specification:

To design the specification you need few basic things to know, about the targeted product, as

1. Function: What is expected from the ASIC or what it supposed to do? So, here you will decide the functionality of the product at top level hierarchy.
2. Performance: What will be the speed, how much power it will consume, how much silicon area it’ll take to implement?
3. I/O requirements: How will the ASIC fit together with the system? So you need to get the requirements of the Inputs and Outputs.
4. Special Requirements (if any): If the targeted product has any special requirement like Low Power, or has some specific parameters to fit in. In that case we need to define our specification in that manner.

Feasibility Check:

So now you have designed the specifications but are they feasible?

You need to cross check all of the specifications very carefully with all of your project constraints (Cost, Design Time, etc.) to reduce the chances of failure.

Since, in the VLSI industry, in most of the cases, you’ll find the condition of “no back looking” .

1. For most of the projects the condition is “we have never done it, so we don’t know exactly”.

2. Since, we have experience from earlier projects, so we can make small experiments to estimate performance and can choose appropriate technology.

Once we get confirmed with the feasibility checks, then only we can proceed further.

After getting the specification, now it’s the time to act. So once you have the specs then you need to decide the way that in how many ways you can achieve it, and which one is the best suitable way.

When it comes to the suitability, then it includes everything, from Risks to Cost, Time to chances of Failure.

Whole process has lots of complication and in the same time, Time to Market factor is also there. So you need to be very careful while deciding the way to achieve.

Design of Architecture:

As you know, in the whole flow there are so many steps and in so many ways we can achieve the goal in better way.

Here I am taking the most common flow of a small design, but during while, will discuss all related issues and after that we’ll see the bigger picture of the ASIC, that is SOC.

So first you design the Block at schematic level by using various combinational and sequential elements. And then you check it on simulation tools, by passing various test cases. And then you proceed further.

But this can be also done with just an idea of implementation on paper with the help of block diagrams and then we start with HDL, i.e. Hardware Description Languages.

Block Diagram:

It is an iterative process. For that we need to follow some steps, they are

1. Identify blocks: First we should get all the required information to perform the functionality.
   
2. Visualize structure: Now determine the various connections between the blocks.
   
3. Critical paths: Determine the blocks, which are most critical in terms of speed, area or power.
   
4. Divide and Conquer: Draw sub-block diagrams with more details.

During the architectural transformations, we need to take care of the overall efficiency of the design, which is based on the performance parameters:

1. Area (mm2)
   
2. Clock rate (MHz)
   
3. Throughput (data/sec)
   
4. Latency (num clock cycles)

Parallelization:

If we consider the parallelization in the design to achieve the targeted efficiency, that will result in more computations, with increase in area and throughput but clock and latency will not change.

For example:

If we use two parallel blocks, that will result in

1. Double area
   
2. Double throughput
   
3. Same clock
   
4. Same latency

Pipelining:

If we are consider the pipelining, then that will increase the speed of the computation, with increased area, clock, throughput and latency.

For example:

If we introduce one pipeline stage, that will result in

1. Little increase in area
   
2. Double clock
   
3. Double throughput
   
4. Double latency

Iterative Decomposition:

If we consider the iterative decomposition in the design, that will take more clock cycles but in lieu of that we will be able to achieve some good results in terms of area and throughput.

For example:

If we can perform the operation in two iterations, then

1. Area halves
   
2. Clock stays same
   
3. Throughput halves
   
4. Latency doubles

Please Pay Attention:

It's a bit difficult to make questions and keep answering those. Better, Please put your queries and suggestions as comment here or mail me at vlsihelio@gmail.com and get the answers by the next weekend.

Since i also keep updating both of the other blogs, i.e. Physical Design (VLSI - ASIC) & STA - Static Timing Analysis (VLSI - ASIC), along going through my hectic work schedule, with new posts. So, usually, i run out off time.

As far as Industry oriented questions and issues are concerned, i'll keep updating you, as soon as i'll get some time for the same.

Note: Before putting queries, please have a look of both of these blogs, may be the answers are already there.

Physical Design (VLSI - ASIC)
STA - Static Timing Analysis (VLSI - ASIC)