Basic STA Part-3

Net and Cell Timing Arcs:

The actual path delay is the sum of net and cell delays along the timing path

Net/Interconnect Delay and Cell/Gate Delay:

“Net/Interconnect Delay” refers to the total time needed to charge or discharge all the parasitics of a given net.

Total net parasitics are affected by

1. Net length

2. Net fanout

“Cell/Gate delay” refers to the total time needed to reach the signal from cell input the output

Total cell delay affected by

1. Slew rate

2. Input Capacitance

Net Delay Calculation:

Prior routing stage we use Wire Load Model to estimate the delay and after routing we use the real post routed delay information for static timing analysis.

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it.

It comes from your library or from a floorplanning tool. It is the method to initially estimate your delays and is usually overly pessimistic.

Cell Delay Calculation

Prior to Routing, cell delays are calculated from tables in the technology library. The tables are commonly indexed by input transition versus total output loading

For Example: As shown in below figure, if input transition is of 0 ns and the total output load is 0.4 fF, then the cell delay will be 6 ps.

Now you know how we do the pre-layout STA and from where we get the delay values. But can you compare it with post layout STA and why we do that?

Here few things are mentioned, I think quite enough to start thinking. Later on, we’ll discuss this in detail.

Clock Source latency and Network latency

So the Clock source latency is the delay from the oscillator to the clock pin of the chip, and the Clock network latency is the delay between the clock pin of the chip to the flop.

Slack

Slack is generally defined as the difference between the Required Times (RT) and Arrival Times (AT) at an end point.

Arrival time means actual value of time getting by tool from from level one to end of level

Required arrival time (RT) is the time before which a signal must arrive to avoid a timing violation.

STEP1: Calculate timing level for each node

STEP2: Calculate AT from level 1 to level n

Assumptions:

1. Input arrival time of 1
   
2. Wire delay 0.2, cell delay 0.5
   
3. Blue colored numbers are showing levels.
   
4. Green colored numbers are showing Arrival times.
   
5. Red colored numbers are showing Required times.
   
6. Purple colored numbers are showing respective Slacks.

Calculation of RT from level n to level 1

Assumptions:

Output required time of 2.8

Gate delay 0.5, wire delay 0.5

Calculation of Slack

Slack =RT –AT

Rectification of Violations:

There are so many methods and methodologies which are followed by the tools and the designers.

Few of them are mentioned here. Don’t predict that these all methods are followed by the designer itself, nowadays tools are smart enough to use these to meet timings.

Swapping pins:

Swap connections on cumulative pins or among equivalent nets. As you can see in the below given example, how it helps to meet timings.

Resize cell:

1. Up size: If fan-out and Capacitance loading is more
   
2. Down size: If fanout and load is less.

Buffering:

We use buffering at various stages in the whole flow, so many times,

1. To improve the signal strength
2. To provide delay

Cloning:

Cloning is a good method to distribute the load and to improve the signal strength.

Re-design Fanout Tree:

This method is also used to meet timing, as you can see the longest path in the first design is of 5 (top most, in right side of both design, AND is of 3). But by redesigning it, we can achieve the longest path of 4.

Re-design Fan-in Tree:

Decomposition:

Requirements in the perspective of EDA tools:

Inputs & Outputs of STA

Inputs

Netlist (.v): The gate level netlist, having circuit description.

1. Constraints (.sdc): Synopsys Design Constraint file. It contains all the timing related information about the design. Includes the Clock definition (Created clock, generated clock, Virtual clock), Uncertainty (Jitter, Skew, Extra margin), IO Delays, False paths, Multi-cycle paths, Max trans, Max fanout, Max cap, Fanout load.
2. SDF (.sdf): Standard Delay Format File containing back-annotated delays.

OR

4. Standard Parasitic Exchange Format (.spef): These are the parasitic of the design extracted from physical design tools.
5. Liberty File (.lib): The delay model of every cell in the library.

• Outputs

Reports: Different timing paths reports, which can be used for debugging.

Various tools used in STA

1. Prime Time (PT) - Synopsys

2. Design Time (DT) - Synopsys

3. Nano Time - Synopsys

4. Path Mill - Synopsys

5. ETS - Cadence

6. Pearl - Cadence

7. Velocity - Mentor Graphics

8. Eins Timer - IBM

9. Eins TLT - IBM

10. Motive - Viewlogic (Now owned by Synopsys)

11. Time Craft - Incentia