VLSI - ASIC FLOW - Part-2

I think, anybody who is going to start the ASIC flow should know the Characteristics of the Good ASIC Design Flow.

Characteristics of Good design flow:

1. Design flow should have the flexibility to deal with the new challenges, which keep coming with changing technology, with minimum changes in it.
2. As the EDA industry is also growing, new tools are emerging at an accelerated speed, so the design flow should have the ability to absorb the latest developments easily.
3. Design flow should also have the capability of handling large, complicated designs and small, simpler designs differently.
4. There should be flexibility to allow some major steps to be executed on their own or outside of the flow, as place n route, sta, etc.
5. Design flow should be friendly to engineering change order (ECO).
6. Check function of the design flow must be robust, sometimes even at the expense of efficiency.

Design of Specification:

To design the specification you need few basic things to know, about the targeted product, as

1. Function: What is expected from the ASIC or what it supposed to do? So, here you will decide the functionality of the product at top level hierarchy.
2. Performance: What will be the speed, how much power it will consume, how much silicon area it’ll take to implement?
3. I/O requirements: How will the ASIC fit together with the system? So you need to get the requirements of the Inputs and Outputs.
4. Special Requirements (if any): If the targeted product has any special requirement like Low Power, or has some specific parameters to fit in. In that case we need to define our specification in that manner.

Feasibility Check:

So now you have designed the specifications but are they feasible?

You need to cross check all of the specifications very carefully with all of your project constraints (Cost, Design Time, etc.) to reduce the chances of failure.

Since, in the VLSI industry, in most of the cases, you’ll find the condition of “no back looking” .

1. For most of the projects the condition is “we have never done it, so we don’t know exactly”.

2. Since, we have experience from earlier projects, so we can make small experiments to estimate performance and can choose appropriate technology.

Once we get confirmed with the feasibility checks, then only we can proceed further.

After getting the specification, now it’s the time to act. So once you have the specs then you need to decide the way that in how many ways you can achieve it, and which one is the best suitable way.

When it comes to the suitability, then it includes everything, from Risks to Cost, Time to chances of Failure.

Whole process has lots of complication and in the same time, Time to Market factor is also there. So you need to be very careful while deciding the way to achieve.

Design of Architecture:

As you know, in the whole flow there are so many steps and in so many ways we can achieve the goal in better way.

Here I am taking the most common flow of a small design, but during while, will discuss all related issues and after that we’ll see the bigger picture of the ASIC, that is SOC.

So first you design the Block at schematic level by using various combinational and sequential elements. And then you check it on simulation tools, by passing various test cases. And then you proceed further.

But this can be also done with just an idea of implementation on paper with the help of block diagrams and then we start with HDL, i.e. Hardware Description Languages.

Block Diagram:

It is an iterative process. For that we need to follow some steps, they are

1. Identify blocks: First we should get all the required information to perform the functionality.
   
2. Visualize structure: Now determine the various connections between the blocks.
   
3. Critical paths: Determine the blocks, which are most critical in terms of speed, area or power.
   
4. Divide and Conquer: Draw sub-block diagrams with more details.

During the architectural transformations, we need to take care of the overall efficiency of the design, which is based on the performance parameters:

1. Area (mm2)
   
2. Clock rate (MHz)
   
3. Throughput (data/sec)
   
4. Latency (num clock cycles)

Parallelization:

If we consider the parallelization in the design to achieve the targeted efficiency, that will result in more computations, with increase in area and throughput but clock and latency will not change.

For example:

If we use two parallel blocks, that will result in

1. Double area
   
2. Double throughput
   
3. Same clock
   
4. Same latency

Pipelining:

If we are consider the pipelining, then that will increase the speed of the computation, with increased area, clock, throughput and latency.

For example:

If we introduce one pipeline stage, that will result in

1. Little increase in area
   
2. Double clock
   
3. Double throughput
   
4. Double latency

Iterative Decomposition:

If we consider the iterative decomposition in the design, that will take more clock cycles but in lieu of that we will be able to achieve some good results in terms of area and throughput.

For example:

If we can perform the operation in two iterations, then

1. Area halves
   
2. Clock stays same
   
3. Throughput halves
   
4. Latency doubles