SDF stands for the “Standard Delay Format”.
It stores the timing data generated by EDA tools for use at any stage in the design process. It can be used anywhere in the flow as to import or export the timing information about design.
The data in the SDF file is represented in tool independent way and can include:
- Delays: Module path delay, device delay, interconnects delay and port delay.
- Timing checks: Setup, hold, recovery, removal, skew, width, period and no change.
- Timing constraints: Path, skew, period, sum and diff.
- Timing environment: Intended operating timing environment.
- Incremental and absolute delays.
- Conditional and unconditional module path delays and timing checks.
- Design/Instance specific or type/library specific data.
- Scaling, environmental and technology parameters like, Process variations, temperature, voltage and wire load models.
Throughout the design process, you can use several different sdf files. Some of these files can contain pre layout timing data. Others can contain path constraint or post layout timing data.
The name of each sdf file is generated (determined) by EDA tool. There are no conventions for naming SDF files.
