Netlistless floorplan is a dummy floorplan with all available information and guesses by the previous experiences, to have a look into the possible coming difficulties in making the chip a way to Fab.
Generally we start this activity at the stage of synthesis. When the synthesis is going on, at the same time the team comes up with a rough floorplan. Generally the design related strategies get almost completed by the time of synthesis, anyway the possibility of minor changes are always there and at any stage.
As in any big design generally there will be memory blocks, some big or small hard and soft macros and like this some more blocks where we know there will not be much changes in their shapes and positions, so now we can come up with a rough floorplan. Obviously there will be a lot of changes in the whole floorplan afterwards but just to keep ourselves always ready for the worst situations we use to have a look into the future in various ways n aspects.
Since the things are still not completed so the tools will give alots of error in analyzing the things but at that time you need to know that why it’s coming and if possible then make some temporary fixes and proceed. Some times we cheat the tools also by various ways.
We generally use this netlistless floorplan for power planning and afterward, static IR drop analysis, just to have an idea about the problems which may screw the things badly.
Showing posts with label PD. Show all posts
Showing posts with label PD. Show all posts
September 20, 2008
June 27, 2008
What is the Physical Design? What are the various steps included in the whole process?
"Physical Design" includes all the tasks needed to build a silicon chip from design netlist to final GDSII layout.
Compared to design capture, simulation, and logic synthesis (which are called front-end activities), physical design is referred to as back-end work.
In other words, physical design covers the tasks necessary to turn the design from a logic entity into a physical entity. It starts from the netlist, which is generated from the logic synthesis. However, the physical design can also include the task of RTL logic synthesis since there is an ever-increasing tie between the logic synthesis and the physical layout. The term physical synthesis reflects this fact.
The list below shows roughly the major tasks in the physical design domain:
Compared to design capture, simulation, and logic synthesis (which are called front-end activities), physical design is referred to as back-end work.
In other words, physical design covers the tasks necessary to turn the design from a logic entity into a physical entity. It starts from the netlist, which is generated from the logic synthesis. However, the physical design can also include the task of RTL logic synthesis since there is an ever-increasing tie between the logic synthesis and the physical layout. The term physical synthesis reflects this fact.
The list below shows roughly the major tasks in the physical design domain:
- Logic synthesis
- DFT insertion
- Electric rules check (ERC) on gate-level netlist
- Floorplan
- Die size
- I/O structure
- Design partition
- Macro placement
- Power distribution structure
- Clock distribution structure
- Preliminary check
- IR drop
- ESD
- EM
- Place and route
- Parasitic extraction and reduction
- SDF generation
- Various checks
- Static timing analysis
- Cross talk analysis
- IR drop analysis
- Electron migration analysis
- Gate oxide integrity check
- ESD/latch-up check
- Efuse check
- Antenna check
- Final layout generation
- Manufacturing rule check, LVS check
- Pattern generation
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