What is the netlistless floorplan? And what is the use of it?

Netlistless floorplan is a dummy floorplan with all available information and guesses by the previous experiences, to have a look into the possible coming difficulties in making the chip a way to Fab.
Generally we start this activity at the stage of synthesis. When the synthesis is going on, at the same time the team comes up with a rough floorplan. Generally the design related strategies get almost completed by the time of synthesis, anyway the possibility of minor changes are always there and at any stage.
As in any big design generally there will be memory blocks, some big or small hard and soft macros and like this some more blocks where we know there will not be much changes in their shapes and positions, so now we can come up with a rough floorplan. Obviously there will be a lot of changes in the whole floorplan afterwards but just to keep ourselves always ready for the worst situations we use to have a look into the future in various ways n aspects.
Since the things are still not completed so the tools will give alots of error in analyzing the things but at that time you need to know that why it’s coming and if possible then make some temporary fixes and proceed. Some times we cheat the tools also by various ways.
We generally use this netlistless floorplan for power planning and afterward, static IR drop analysis, just to have an idea about the problems which may screw the things badly.