In most of the design, generally memory block has very less time margin to meet setup or hold requirements, then how you'll be able to meet timings?

By putting a latch before the memory or you can say by applying "time borrowing" concept.
But still designers don’t prefer in simple designs to place latch everywhere, where they are not meeting timings, since then analysis will be more complicated.

Next Question:
What is the netlistless floorplan? And what is the use of it?
Get the answer in detail by next weekend (15th Aug), till then think over it.

What is the Physical Design? What are the various steps included in the whole process?

"Physical Design" includes all the tasks needed to build a silicon chip from design netlist to final GDSII layout.

Compared to design capture, simulation, and logic synthesis (which are called front-end activities), physical design is referred to as back-end work.

In other words, physical design covers the tasks necessary to turn the design from a logic entity into a physical entity. It starts from the netlist, which is generated from the logic synthesis. However, the physical design can also include the task of RTL logic synthesis since there is an ever-increasing tie between the logic synthesis and the physical layout. The term physical synthesis reflects this fact.

The list below shows roughly the major tasks in the physical design domain:

1. Logic synthesis
2. DFT insertion
3. Electric rules check (ERC) on gate-level netlist
4. Floorplan
5. Die size
6. I/O structure
7. Design partition
8. Macro placement
9. Power distribution structure
10. Clock distribution structure
11. Preliminary check
12. IR drop
13. ESD
14. EM
15. Place and route
16. Parasitic extraction and reduction
17. SDF generation
18. Various checks
19. Static timing analysis
20. Cross talk analysis
21. IR drop analysis
22. Electron migration analysis
23. Gate oxide integrity check
24. ESD/latch-up check
25. Efuse check
26. Antenna check
27. Final layout generation
28. Manufacturing rule check, LVS check
29. Pattern generation

Regarding SKEW and CLK Timeperiod

On Thu, May 22, 2008 at 9:32 PM, helio vlsi <vlsihelio@gmail.com> wrote:

Hi *******,
Yes, its possible. Your skew can be greater than clock period.

But i think you'll never able to see it in your design, until unless you make the design purposefully to give that much of skew or when someone do the CTS, who doesn't know it at all.

No tool will give you that much of skew, until unless you are forcing it to do like that.

But STA tool will take that in different manner, and it will not recognize that much of skew. Simply it will do the analysis on the previous edges.

Ok, do one thing, take a clock as reference and then take another one which is delaying by more than a clock. And then do the setup & hold check. Analyze the various scenarios by shifting it in left n right, i think u'll get the point.

Don't forget, tool doesn't understand anything until unless you aren't defining it in constraints.

Try n get back if still you have any doubt in your mind.
Thanks for query.

Regards
Helio

On Wed, May 21, 2008 at 1:16 PM, ****** <**********@gmail.com> wrote:

Hi helio,

I am ******. I have doubt in STA.
Is there any chance of clock skew being greater than or equal to the timeperiod of the clock? If so,what are the effects?

Any help would greatly appreciated.
Thanks in advance.

--
" I don't have the LICENSE to kill ;
But then again I can't change my looks."


lots of love

******