INTRODUCTION TO ASIC - Part-1

Evolution of VLSI:

What is an ASIC?

• Application-specific integrated circuit

• Customized for a particular use customized for a particular use, rather than intended for general-purpose use

• For example, a chip designed solely to run a cell phone is an ASIC. [Not ASICs: General-purpose processors, memory chips and other standard components]

•Dedicated to single function, or limited range of functions.

•A typical ASIC is a circuit, where functions are designed by the customer and layout and the fabrication is done by the silicon vendor.

•Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

•The maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million

Types of ASIC:

1. Full Custom ASICs

2. Standard Cell Based ASICs (CBIC)

3. Gate Array Based ASICs

3. a. Channeled Gate Array

3. b. Channel-less Gate Array

3. c. Embedded Gate Array

4. Programmable Logic Devices

4. a. Field Programmable Gate Arrays

4. b. Complex PLD (CPLD)

Full Custom ASIC:

• In a full-custom ASIC, an engineer designs some or all of the logic cells, circuits, or layout specifically for one ASIC. This means the designer abandons the approach of using pre-tested and pre-characterized cells for all or part of that design.

• It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design. This might be because existing cell libraries are not fast enough, or the logic cells are not small enough or consume too much power.

• Hand drawn geometry and all layers are customized.

• Can be used for both, Digital and analog.

• High density, High performance & Long design time.

Standard Cell Based ASIC (CBIC):

• A cell-based ASIC (cell-based IC, or CBIC uses pre-designed logic cells (AND gates, OR gates, multiplexers, and flip-flops, for example) known as standard cells.

• The advantage of CBICs is that designers save time, money, and reduce risk by using a pre-designed, Pre-tested, and pre-characterized standard-cell library

• Standard cells organized in rows (and, or, flip-flops, etc.)

• Cells made as full custom by vendor (not user).

• Medium- high density, Medium-high performance & Reasonable design time.

• All layers are customized.

Standard Cell:

• Cells are configured in rows and have constant height and variable width.

• Each cell is optimized for an efficient implementation.

Gate Array:

• A gate array chip contains prefabricated adjacent rows of PMOS and NMOS transistors.

• The gate array is configured by the interconnect structure.

• Predefined transistors connected via metal

• Only metal layers customized

• Fixed array sizes (normally 5-10 different)

• Digital cells in library (and, or, flip-flops, etc.)

• Simulation at gate level (digital)

• Medium density & Medium performance

• Reasonable design time

Channeled Gate Array:

• Only the interconnect is customized.

• The interconnect uses spaces between rows of base cells

Channel-less Gate Array (Sea of Gates):

• Only the interconnect is customized.

• Cells are connected via unused transistors

Embedded Gate Array:

• Only the interconnect is customized.

• Custom Blocks can be embedded.

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