INTRODUCTION TO ASIC - Part-2

Field Programmable Gate Arrays:

• None of the layers is customized.

• Basic logic cells and interconnect can be programmed.

• Basic cells can be SRAM based, Flash Memory based or fuse-based (One time programmable)

Advantages & Disadvantages of FPGA:

Advantages:

• A shorter time to market

• Ability to re-program in the field to fix bugs

• Lower non-recurring engineering costs

• For smaller designs and/or lower production volumes, FPGAs are more cost effective than an ASIC design.

Disadvantages:

• Usually slower than their ASIC & Cannot handle a complex design

• Draw more power.

• No layers customized (standard devices) & Can be used for Digital only

Complex Programmable Logic Device (CPLD):

• A CPLD is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both.

• No customized mask layers or logic cells.

• A single large block of interconnects.

• Macro-cells consist of programmable array logic followed by a flip flop or latch.

• A CPLD has non-volatile configuration memory like PALs.

• Unlike many FPGAs, an external configuration ROM isn't required

• CPLD can function immediately on system start-up.

Features in common with FPGAs:

• Large number of gates available.

• Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic.

• The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD

• As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur

Comparison:

Advantages of ASIC:

• Reducing the size of your finished product, i.e. consumes reduced area compared to their counterparts.

• Allowing you to include greater functionality.

• Assembly cost is reduced and reliability is increased.

• Removes the need for in-house testing of a substantial part of the circuit.

• Power consumption of a single chip is normally far less.

• Design security.

• ASIC has more speed compared to CPLD and FPGA.

Disadvantages of ASIC:

• Requires a higher level of commitment both financially and technically at a relatively early stage in the development of a project.

• Level of risk is too much high at every stage of chip Designing.

• High Non Recurrent Engineering (NRE) cost.

• Much higher skill requirement on the part of the design team.

• The cost of development and Time to market is more for ASIC.

Packaging of ASIC:

The various types of IC Packaging are:

Flip Chip, Wire Bond, Multi chip Module (MCM), Chip Scale Package (CSP), Quad Flat Packs (QFP), Stacked Die Packages, Ball Grid Array Packages (BGA), Land Grid Array (LGA), SiP, Quad No-lead Packages (QFN), Plastic Leaded Chip Carriers (PLCC), SO, SOT, TSOP, WLP.

The metric to select the packaging are:

• Cost (Should be Less) & Reliability

• Form factor (Packing Density)

• Performance {Simultaneous Switching Noise, Signal Propagation, Power ground distribution}

• Thermal (Efficient heat removal) and Electrical (Low parasitic) Enhanced

Wire Bond:

• Flexible, Cost effective & Suitable for limited number of pads

• Only periphery of chip available for IO connections

• Mechanical bonding of one pin at a time (sequential)

• Cooling from back of chip

• High inductance (~1nH) & Capacitance (~1pF)

Challenges involved in Wire bonding:

• Reduction in Wire Diameter

• Wire length Increase

• Loop height minimum achievable

• Wire Bond pitch reduction (pitch-range is of 60u)

• Pad Size Opening reduction & BGA Package total height reduction

Flip Chip (Controlled Collapse Chip Connection, or C4):

• The final wafer processing step deposits solder bumps on the chip pads, which are used to connect directly to the associated external circuitry.

• Does not require any wire bonds

• Good Power and Ground Distribution possible.

• With the Area array more I/O density is possible.

• Low stress over active area.

• Targeted for High device speed.

• Low Inductance (~0.1nH) & Capacitance (~0.5pF)

• Costlier.

• Production area array pitch around 178 micron.

• Whole chip area available for IO connections

• Automatic alignment

• One step process (parallel)

• Cooling via balls (front) and back if required

• Thermal matching between chip and substrate required

Future Technologies:

• WLBI (Wafer Level Burn in)

• Optical Interconnects

• Multiple Die-Stacking

Next Post: Complete VLSI flow with each and every details of various steps.