BASIC STA Part-1

Timing Analysis:

Timing analysis is necessary to calculate the design’s system performance, describes the chips specification, accounts for chip pad loading, helps in achieving clock speed and above all of the reasons, determines if the chip works in two contrast places, like Sahara and Switzerland.

Types of timing analysis:

1. Dynamic timing analysis (DTA)

2. Static timing analysis (STA)

Dynamic Timing Analysis (Gate level Simulation):

A series of vectors over a time are applied during a simulation run, simulation calculates the logic value and delays over that time. So, in that manner we check the design’s functionality with time.

Static Timing Analysis:

Static timing analysis is a method for determining if a circuit meets timing constraints without having to simulate.

So, it validates the design for desired frequency of operation, without checking the functionality of the design.

Comparison of Analysis

Dynamic timing

1. Requires exhaust set of vectors
2. Checks for both functional and timing problems
3. Requires more resources like run time, CPU memory, etc.
4. Can work with any type of Logic either synchronous or asynchronous
5. Slower as compared to STA.
6. Easy to learn

Static timing

1. Doesn't requires any set of vectors.
2. Checks for timing only.
3. Requires fewer resources than DTA.
4. Restricted to synchronous part of the design only.
5. Faster as compared to DTA.
6. Difficult to learn

Why Static timing Analysis?

1. To analyze the timing relationships of a given circuit to verify that the circuit works at the specified frequency (verification).
2. 100 % path coverage is possible because no design specific pattern is required.
3. You can’t achieve the clock speed without it.
4. All paths are assumed critical.
5. Process variation across die can be modeled.
6. Constraints and reports are concise and easy to interpret.
7. It can detect other serious problems like glitches, slow paths and clock skew.

Note: This analysis is done to provide the engineer feedback in order to help modify the design and/or modify the constraints to improve the timing quality of the design.

Place of STA in the ASIC Flow

STA involves three main steps:

1. Design is broken down into sets of timing paths.
2. Delay of each path is calculated.
3. Path delays are checked to see if timing constraints have been met.

But first some Basic STA concepts:

Timing Paths:

Each path has a startpoint and an endpoint

1. Startpoints:

Input ports (A, Q)

Clock pins of sequential devices (CLk)

2. Endpoints:

Output ports (D, Z)

Data input pins of sequential devices (D)

Basic Timing Paths

Generally recognizes five types of default timing paths:

1. Clock to setup
2. Clock to pad
3. Pad to pad
4. Pad to set up

Clock to setup:

A clock to setup path starts at flip flop clock inputs, propagates through the flip flop Q out put and any number of levels of combinational logic, and ends at non clock flip flop register inputs.

Clock to pad:

It starts at a clock input of a flip-flop, propagates through the flip-flop Q output and any number of levels of combinational logic, and ends at an output pad.

Pad to Pad :

A pad to pad path starts at an input of the chip, propagates through one or more levels of combinational logic, and end at an output pad of the chip.

Pad to Setup:

A pad to setup path starts at an input pad of chip and ends at flip flop input.