VLSI - ASIC FLOW - Part-1

Where it all got started?

Existence of “NEED” assures MARKET and so CUSTOMERS, DEMAND and SUPPLY.

And this force drives everything including our technology also.

In VLSI industry, “Time to Market” is the most important factor; you can “DELAY” or “EXIST”.

It’s very rare, when you can have both choices at a time.

Reasons can have a broad spectrum, but the consequences are almost limited to these parameters.

Current scenario of the industry shows that the things have got that much critical & complex, as well, that it’s almost impossible for a single company to get all jobs done, alone.

So they outsource some part of the project, there arises the concept of sub-chip level development.

But in some exceptional cases, there are few companies, who work alone and get everything done in house only.

In ASIC (Application Specific Integrated Circuit) or SOC (System on Chip) implementation, there are two main categories, “ Full custom flow” or “Semi custom flow”.

For the further reading on the same, please refer “ASIC- Sebastian Smith”.

As of now, in short, for Full custom, we need to create a specific library for the targeted product, but in Semi custom we use the already existed library to implement the product.

According to the targeted product the flow keeps changing by time, as well according to the technology.

So the question arises here, what is the difference b/w ASIC and SOC?

Keep scratching your head, I’ll discuss that later, may be in my next post.

Now, Full chip and Sub chip Design. Anyway, while discussing the complete flow I’ll be discussing both of these things relatively.

But as of now, A Full chip can have many Sub chips (Macros/Blocks).
Here is a rough hierarchy of the chip, hopes will be a bit helpful.

The flow, I am going to consider is:

*ASIC (Full Chip/Sub-chip)/SOC

1. Specification
2. Architecture
3. Lib Preparation
4. IP implementation/Reuse and Rtl Coding
5. Simulation & Verification
6. Synopsys Design Constraints (SDC)
7. Synthesis
8. Design for Testability (DFT)
9. Static Timing Analysis (STA)
10. Floorplanning
11. Power planning
12. Placement
13. Clock Tree Synthesis (CTS)
14. Routing
15. RC Extraction
16. Design Rule Check (DRC) & Layout Vs Schematic (LVS)
17. Post Route STA
18. Signal Integrity (SI) Analysis
19. IR drop Analysis
20. Noise Analysis
21. Signoff

Note: I have tried to keep every necessary part of the design in the flow. But even though, if you think some thing else should also be added, then, please let me know via comments.

Before going for the flow, I want to discuss few basic things first.

What is Hardware Design?

Physically implementing an idea, a function and a system in hardware.
For any such kind of implementation we need to find the optimal balance between:

1. Cost / Area
2. Speed / Throughput
3. Energy Consumption / Power Density
4. Design Time

Trade-offs in Design

In the design, if you want any thing more specific then usually you need to sacrifice or, you can say, compromise with some other parameters.
So, there’s “No free lunch”.

Depending on the design, some parameters are more important and some are less.
So, you can generally sacrifice one parameter to improve the other:

1. Speed vs Area: It is possible to speed up a circuit by using larger transistors, parallel computation blocks, but then it will take more area.

2. Design time vs Performance: If we are with enough time to design, then the circuits can be optimized for higher Performance.

So, finally you need to make a lot of trade offs in the whole process of design, with different parameters like, speed, area, power, etc.

When to use ASICs?

As in the earlier posts, I have discussed the pros & cons of the ASIC. So, here just I am going in brief.

The pros:

1. Highest performance
2. Cheap for mass production

The cons:

1. Long development time
2. Not very configurable
3. Requires specialization

So overall, it depends upon our targeted product, whether we should go for the ASIC or FPGA or CPLD, etc.