BASIC STA Part-2

Timing Violations:

• Setup or Hold violation:

1. Leads to improper operation of the flip flop and the connected components, it can result in missed data or ignored actions.
2. The output of the flip flop goes into a state of metastability in the case of Setup/Hold violations.

• Recovery and Removal Violations :

1. Violations of Preset and Clear signal with respect to the Clock.

Setup Time:

• The time required for the input data to be stable before the triggering clock edge.
• So, Set-up check establishes that the path is fast enough for the desired clock frequency.

Hold Time:

• The time required for the data to remain stable after the triggering clock edge.
• So, hold check ensures that the path is not too fast so that data is not passed through.

Why Setup & Hold?

1. Setup & Hold times are because of the intrinsic delays of the flip flop. Intrinsic delays are the actual delays of the transistors inside the cell.
2. Setup and Hold are the times required for charging the capacitances present inside in cell.

Delay of an Inverter:

t = Rp * C

The delay is decided by the resistance of Pmos and the output capacitance.

The product ‘RC’ is called the “TIME CONSTANT”. This determines the delay of the cell.

When Vo = Logic ‘1’ t = Rn * C

The delay is decided by the resistance of Nmos and the output capacitance.

How to remove Setup & Hold violations:

• To solve setup violation

1. By optimizing and restructuring the combinational logic between the flops of design. In big designs, we dont do this by ourselves, generally tool does this for us. And what are the ways that tool follows for the same? We'll discuss that in next post.

2. By using “Tweak flops” to offer less setup delay. Since, Tweak launch-flop have better slew at the clock pin and this makes CK->Q of launch flop faster, so that it helps in fixing setup violations.

3. By using Useful- skews.

• To solve Hold Violations

1. By adding delay/buffer cell. Since the simple buffer offers less delay, so we use special Delay cells whose functionality remains same, i.e. Y=A, but with more delay.

2. By providing delay to the launch flop clock.

3. Where the hold time requirement is huge, we can use Lock-up Latches also.

Few GOOGLIES for you:

1. What is negative setup? And where we use that?
2. In most of the design, generally memory block has very less time margin to meet setup or hold requirements. In that case how you'll be able to meet the timing?

Note: For more faqs, keep visiting http://vlsifaqs.blogspot.com

STA: Critical terms

1. Critical path: The path between an input and an output with the maximum delay.
2. Recovery time: It is the minimum time that an asynchronous control must be stable before the clock active-edge transition.
3. Removal time: It is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.

Jitter : Variation in period from clock source (PLL)

Insertion Delay

• The delay between the clock root pin and clock sink pin of the flip flop

Glitch- A glitch is a short-lived fault in a system.

• An electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit

Input Delay:

Output Delay:

Single Cycle Paths:

• By default, static timing tools assume all timing paths to be single cycle paths

There could be exceptions defined to the above behavior:

1. Multi-cycle paths
2. False paths

Multi-Cycle Paths:

• Those paths that require more than one clock period for execution are called as multi-cycle paths.

• It’s essential that multi-cycle paths in the design be identified both for synthesis and STA.

False Paths:

• A path that can never be sensitized in the actual circuit
• These paths are those that are logically/functionally impossible
• The goal in static timing analysis is to do timing analysis on all “true” timing paths, these paths are excluded from timing analysis.

Combinational Loop:

• Most STA’s can’t leave combinational loops in the design, because a race condition will occur.

GOOD ONE:
If i am not defining the False or Multicycle paths or Combinational Loops or Input/Output Delay in my constraint file (.sdc). In that case, what can be the effects you will find in your reports? (Analyze this one by one.)

Note: For more faqs, keep visiting http://vlsifaqs.blogspot.com

Clock skews (timing skew):

• Clock signal in synchronous circuits arrives at different components at different times.

Clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Reasons for the Skew:

1. Wire-interconnect length
2. Temperature variations
3. Variation in intermediate devices
4. Capacitive coupling
5. Material imperfections

Two Types of Clock Skew:

1. Negative skew
2. Positive skew

Positive skew:

• Occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Negative skew:

• Is the opposite:- the receiving register gets the clock earlier than the sending register.